1. Field of the Invention
The present invention relates to an integrated circuit device, and more particularly relates to an integrated circuit device having two or more input ports that are each capable of operating independently.
2. Description of Related Art
As the operating frequency of an interface of an integrated circuit device increases, especially that of a memory device, the bus efficiency relatively decreases. A typical memory device generally has an input/output port, which is used for both inputting and outputting of data. In such a typical memory device, the bus efficiency decreases as the operating frequency increases.
Although some memory devices have a separate input port and a separate output port, the input port and the output port are completely separate from each other, and thus the number of pins used increases leading to an undesirable increase in cost.
FIG. 1 is a timing diagram showing data bus efficiency of an integrated circuit device having a single input/output port, indicated generally by the reference numeral 100. The data bus efficiency shown in FIG. 1 corresponds to a case where reading and writing are repeatedly performed at a ratio of three reads to one write. Here, the clock frequency is 200 Mhz, and one clock cycle is thus 5 ns. A write recovery time (“tWR”), which denotes a time necessary for all input data to be written in a memory core, is 10 ns. The column address select (“CAS”) latency (“CL”) is 15 ns, and a burst length (“BL”), which denotes an index indicating the number of data units written in response to one write command, is 4.
R denotes a read command, W denotes a write command, Q denotes read data that is read out in response to the read command, D denotes written data that is written in response to the write command.
Three read commands and one write command are here regarded as one set. The number of clock cycles, from the first set when the first read data is output in accordance with three read commands and one write command, to the second set when the next read data is output in accordance with three read commands and one write command, is 14. The number of clock cycles required for the data to be written or read through the bus is 8. Therefore, the data bus efficiency is 8/14, or about 57 percent.
FIG. 2 is a timing diagram showing data bus efficiency when the integrated circuit device operates at a higher frequency than the integrated circuit device of FIG. 1, indicated generally by the reference numeral 200. Here, the clock frequency is 400 Mhz, and thus one clock cycle is 2.5 n. The CL, BL and tWR are the same as those of FIG. 1.
The number of clock cycles, from the first set when the first read data is output in accordance with three read commands and one write command, to the second set when the next read data is output in accordance with three read commands and one write command, is 19. The number of clock cycles for the data to be written or read through the bus is 8. Therefore, the data bus efficiency is 8/19 , or about 42 percent.
As shown in FIGS. 1 and 2, the turn around time, which is the time required to turn from a write operation to a read operation and back again, or vice versa, increases as the operating frequency of the integrated circuit device increases, and thus the data bus efficiency decreases. Therefore, it is desirable to reduce the number of operations incurring the turn around time.